The field of invention relates to signal processing. More specifically the field of invention relates to an improved interface circuit that employs an indication signal.
Due to advances in silicon technology, the operational speed of various channels continues to increase. For example, in the communications field, traditional Wide Area Network (WAN) channels having data rates under 10 Mb/s (such as T1,/E1 fractional T1 (FT1), x.21, v.35, RS-232, RS-449, RS-532 are being replaced or enhanced by WAN technologies having data rates greater than 10 Mb/s (such as High Speed Serial Interface (HSSI), ADSL, VDSL, DS3 and cable modem).
Even though faster channels are being implemented, however, it is often more economical to preserve (where possible) designs originally used to support legacy channels. That is, in order to implement a new, faster channel technology, it is often more economical to squeeze more bandwidth out of an existing, original design by modest modification rather than introduce a completely new design. Note that, in light of this, although silicon advances support higher data rates; mechanical solutions such as connectors tend to advance slower.
Thus economic advantage is realized in the form of downward compatibility. One aspect of downward compatibility is that higher speed channels may be integrated into products that also support lower speed channels. Products designed with downward compatibility in mind allow: 1) customers to make the transition from lower speed channels to higher speed channels gradually resulting in longer lifetimes for the slower but cheaper traditional channel technologies; and 2) manufacturers to minimize development and manufacturing costs since completely new designs tend take more time to design as well as use new, more expensive materials.
A good, practical example of the notions discussed above concern adapter cards used for networking routers, switches or other networking systems. FIG. 1a shows an example of an adapter card 100 designed for corporate campus environments. A plurality of such cards are typically inserted into the backplane of a campus switch or router. The adapter card 100 example comprises two cards: a base card 101 used for Local Area Network (LAN) connections and a daughter card 102 used for WAN connections. The daughter card 102 plugs into the connector 105 that is affixed to the base card 101. Backplane connector 106 typically passes signals from/to the base and daughter cards 101, 102 to/from a central switching or routing card in the networking system.
FIG. 1b indicates how the card appears to a customer after the card is plugged into a networking system. Note that a single card offers both LAN connections (e.g., ethernet connections via RJ48 connectors 103a,b) and WAN connections (e.g., an X.21 connection via D shell connector 104a,b). Referring back to FIG. 1a, in order to support downward compatibility with respect to the WAN daughter card 102, adapter card 100 should support both older, slower WAN daughter cards as well as newer, faster WAN daughter cards.
This means the electrical signaling that runs through connector 105 must be capable of supporting data rates greater than 10 Mb/s (e.g., a 45 Mb/s DS3 data rate). In order to provide a downward compatible solution, the design of the electrical interface between the base card 101 and daughter card 102 through connector 105 (originally designed to operate at speeds under 10 MB/s (e.g., a 1.5 Mb/s T1 data rate)) must be modified to support slower legacy WAN daughter cards as well as faster, more recent WAN technologies.
FIG. 2 shows an example of an original, legacy interface 200 between the base card 101 and the daughter card 102 used for slower speed WAN channels. In FIG. 2, a single data signal 201 was driven over the connector 205 along with a clock 202 and a gapped clock 203. Other implementations could send the data signal with only a gapped clock 203. Clock 202 is the masterclock for the interface 200 of FIG. 2. Thus, typically, a data value (e.g., at consecutive data values locations 204a,b,c,d) appears on the data signal 201 net per clock 202 tick.
Clock 202 is also typically the masterclock of the card sending the data signal 201. Note that at least two interfaces 200 are implemented across connector 105 of FIG. 1a. That is, referring back to FIG. 1a, the base card 101 sends data to the daughter card 102 across an interface such as interface 200 of FIG. 2. Similarly, the daughter card 102 sends data to the base card 101 across another interface which may be a duplicate of interface 200 of FIG. 2. The gapped clock 203 may be used to identify or select enabled channels within a data stream. For example, gapped clock 203 may be used to identify which 8 kb/s channels within an FT1 line are selected.
The gapped clock 203 may also be used to account for differences between the clocking frequency of the interface masterclock 202 and any other clock used to clock the data stream before being sent over interface 200. For example, referring to FIGS. 1a and 2, consider the case where WAN data is being: 1) received by the daughter card 102 from a network connection, then; 2) delivered from the daughter card 102 across connector 105 to the base card 101 and then; 3) ultimately delivered to a central routing or switching card via backplane connector 106.
In this case, there may be a difference between the clock used by the network to send the data to the daughter card 102 and the masterclock of the daughter card 102 and/or the clock 202 used to transmit the received data over the interface 200 between the daughter card 102 and base card 101. The gapped clock 203 of FIG. 2 accounts for differences between these clocks by occasionally negating a valid data value location in the data signal 201 where the clock differences could otherwise cause corrupted data.
Thus gapped clock 203 is used to indicate which data value locations 204a,b,c,d in the data signal 201 are valid. In the exemplary depiction in FIG. 2, data value locations 204a,b and c are valid while data value location 204d is invalid. This corresponds to the presence or lack thereof of a pulse in the gapped clock 203 signal.
An apparatus comprising a parallel arrangement of circuits is described. Each circuit has a data net input. Each circuit has an indication signal net input configured to transport an indication signal having shapes and/or temporal locations different than a data signal on the data net input.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.